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general description the maxq2000 microcontroller is a low-power, 16-bit device that incorporates a liquid-crystal display (lcd) interface that can drive up to 100 (-rbx) or 132 (-rax) segments. the maxq2000 is uniquely suited for the blood-glucose monitoring market, but can be used in any application that requires high performance and low- power operation. the device can operate at a maximum of either 14mhz (v dd > 1.8v) or 20mhz (v dd > 2.25v). the maxq2000 has 32kwords of flash memory, 1kword of ram, three 16-bit timers, and one or two universal synchronous/asynchronous receiver/transmitters (uarts). flash memory aids prototyping and low-vol- ume production. the microcontroller core is powered by a 1.8v supply, with a separate i/o supply for optimum flexibility. an ultra-low-power sleep mode makes these parts ideal for battery-powered, portable equipment. applications medical instrumentation battery-powered and portable devices electrochemical and optical sensors industrial control data-acquisition systems and data loggers home appliances consumer electronics thermostats/humidity sensors security sensors gas and chemical sensors hvac smart transmitters features ? high-performance, low-power, 16-bit risc core dc to 20mhz operation, approaching 1mips per mhz dual 1.8v core/3v i/o enables low power/flexible interfacing 33 instructions, most single cycle three independent data pointers accelerate data movement with automatic increment/decrement 16-level hardware stack 16-bit instruction word, 16-bit data bus 16 x 16-bit, general-purpose working registers optimized for c-complier (high-speed/density code) ? program and data memory 32kwords flash memory, mask rom for high- volume applications 10,000 flash write/erase cycles 1kword of internal data ram jtag/serial boot loader for programming ? peripheral features up to 50 general-purpose i/o pins 100/132 segment lcd driver up to 4 com and 36 segments static, 1/2, and 1/3 lcd bias supported no external resistors required spi tm and 1-wire (-rax only) hardware i/o ports one or two serial uarts one-cycle, 16 x 16 hardware multiply/accumulate with 48-bit accumulator three 16-bit programmable timers/counters 8-bit, subsecond, system timer/alarm 32-bit, binary real-time clock with time-of-day alarm programmable watchdog timer ? flexible programming interface bootloader simplifies programming in-system programming through jtag supports in-application programming of flash memory ? ultra-low power consumption 190? typ at 8mhz flash operation, pmm1 at 2.2v 700na typ in lowest power stop mode low-power 32khz mode and divide-by-256 mode maxq2000 low-power lcd microcontroller ______________________________________________ maxim integrated products 1 rev 2; 12/04 for pricing, delivery, and ordering information, please contact maxim/dallas direct! at 1-888-629-4642, or visit maxim? website at www.maxim-ic.com. ordering information typical operating circuit and pin configurations appear at end of data sheet. part temp range program memory data memory lcd segments external interrupts uarts pin- package MAXQ2000-RAX -40? to +85? 32kword flash 1kword sram 132 16 2 68 qfn maxq2000-rbx -40? to +85? 32kword flash 1kword sram 100 14 1 56 tqfn note: some revisions of this device may incorporate deviations from published specifications known as errata. multiple revisions of any device may be simultaneously available through various sales channels. for information about device errata, go to: www.maxim-ic.com/errata . maxq is a trademark of maxim integrated products, inc. spi is a trademark of motorola, inc. 1-wire is a registered trademark of dallas semiconductor corp.
maxq2000 low-power lcd microcontroller 2 _____________________________________________________________________ absolute maximum ratings electrical characteristics (v dd = v dd(min) to v dd(max) , v ddio = 2.7v to 3.6v, t a = -40? to +85?.) (note 1) stresses beyond those listed under ?bsolute maximum ratings?may cause permanent damage to the device. these are stress rating s only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specificatio ns is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. voltage range on any pin relative to ground except v dd ................................. -0.5v to (v ddio + 0.5)v voltage range on v dd relative to ground .........-0.5v to +2.75v voltage range on v ddio relative to ground........-0.5v to +3.6v operating temperature range ...........................-40? to +85? storage temperature range .............................-65? to +150? soldering temperature ....................see ipc/jedec j-std-020 ................................................................................. specification parameter symbol conditions min typ max units 32k x 16 flash 1.8 2.5 2.75 core supply voltage v dd flash programming 2.25 2.5 2.75 v i/o supply voltage v ddio v dd 3.6 v i dd1 /1 mode 6.0 9.2 i dd2 /2 mode 5.6 8.6 i dd3 /4 mode 3.4 5.1 i dd4 /8 mode 1.9 2.9 i dd5 pmm1 mode 0.5 0.7 active current, f hfin = 14mhz (note 2) i dd6 pmm2 mode; 32kin = 32.768khz 4.8 7.6 ma i dd1 /1 mode 6.5 10.4 i dd2 /2 mode 5.9 9.6 i dd3 /4 mode 3.8 6.2 i dd4 /8 mode 2.2 3.8 i dd5 pmm1 mode 0.6 1.4 active current, f hfin = 20mhz (note 2) i dd6 pmm2 mode; 32kin = 32.768khz 4.8 8.1 ma execution from flash memory, 20mhz, v dd = 2.2v, t a = +25? 5.1 execution from flash memory, 8mhz, /8 mode, v dd = 2.2v, t a = +25? 0.85 execution from flash memory, 8mhz, pmm1 mode, v dd = 2.2v, t a = +25? 0.19 execution from ram, 8mhz, /8 mode, v dd = 2.2v, t a = +25? 0.30 active current execution from ram, 1mhz, /1 mode, v dd = 2.2v, t a = +25? 0.14 ma -40? < t a < +25? 0.7 55 stop-mode current i stop(vdd) t a = +85? 20 550 ? digital i/o supply current i ddio rtc enabled; hfin 14mhz; all i/o disconnected 150a input high voltage: hfin and 32kin v ih1 0.75 x v ddio v ddio v
maxq2000 low-power lcd microcontroller _____________________________________________________________________ 3 electrical characteristics (continued) (v dd = v dd(min) to v dd(max) , v ddio = 2.7v to 3.6v, t a = -40? to +85?.) (note 1) parameter symbol conditions min typ max units input high voltage: p6.4?6.5 and p7.0?7.1 v ih2 svs on, v lcd = 3.3v 0.75 x v ddio v lcd v input high voltage: all other pins v ih3 0.75 x v ddio v ddio v input low voltage: hfin and 32kin v il1 0 0.2 x v ddio v input low voltage: all other pins v il2 0 0.25 x v ddio v output high voltage: p6.4?6.5 and p7.0?7.1 v oh1 svs on; i oh ( max ) = 0.75ma; v lcd = 2.7v v lcd - 0.2 v output high voltage: all other pins v oh2 i oh(max) = 0.75ma; v ddio =1.8v v ddio - 0.2 v output low voltage for all other pins v ol1 i ol = 1.0ma; v ddio = 1.8v gnd 0.2 v output low voltage for p6.4?6.5 and p7.0?7.1 v ol2 i ol = 1.4ma; v ddio = 2.7v gnd 0.2 v input leakage current i l internal pullup disabled -100 +100 na input pullup current i ip internal pullup enabled -20 -5 ? lcd interface lcd reference voltage v lcd 2.7 3.3 3.6 v lcd bias voltage 1 v lcd1 1/3 bias v adj + 2/3 (v lcd - v adj )v lcd bias voltage 2 v lcd2 1/3 bias v adj + 1/3 (v lcd - v adj )v lcd adjustment voltage v adj guaranteed by design 0 0.4 x v lcd bias resistor r lcd 100 k ? ?
maxq2000 low-power lcd microcontroller 4 _____________________________________________________________________ electrical characteristics (continued) (v dd = v dd(min) to v dd(max) , v ddio = 2.7v to 3.6v, t a = -40? to +85?.) (note 1) parameter symbol conditions min typ max units external clock source external oscillator, v dd 2.25v 0 20 external oscillator, v dd < 2.25v 0 14 external crystal, v dd 2.25v 3 20 external crystal, v dd < 2.25v 3 14 flash programming, v dd 2.25v 2 20 external-clock frequency f hfin flash programming, v dd < 2.25v 2 14 mhz external-clock period t clcl 48% minimum duty cycle 50 ns 2.25v v dd 2.75v 0 20 system-clock frequency f ck 1.8v v dd 2.75v 0 14 mhz system-clock period t ck 50 ns real-time clock rtc input frequency f 32kin 32khz watch crystal 32.768 khz jtag/flash programming mass erase 200 flash erase time page erase 20 ms flash programming time 2.5 5.0 ms write/erase cycles 10,000 cycles data retention 100 years spi timing spi master operating frequency 1/t mck f ck / 2 mhz spi slave operating frequency 1/t sck f ck / 8 mhz sclk output pulse-width high/low t mch , t mcl t mck / 2 - 25 ns sclk input pulse-width high/low t sch , t scl t sck / 2 ns mosi output hold time after sclk sample edge t moh c l = 50pf t mck / 2 - 25 ns mosi output valid to sample edge t mov t mck / 2 - 25 ns miso input valid to sclk sample edge rise/fall setup t mis 30 ns miso input to sclk sample edge rise/fall hold t mih 0ns
maxq2000 low-power lcd microcontroller _____________________________________________________________________ 5 note 1: specifications to -40? are guaranteed by design and not production tested. note 2: measured on the v dd pin with v dd = 2.75v and not in reset. electrical characteristics (continued) (v dd = v dd(min) to v dd(max) , v ddio = 2.7v to 3.6v, t a = -40? to +85?.) (note 1) parameter symbol conditions min typ max units sclk inactive to mosi inactive t mlh t mck / 2 - 25 ns mosi input to sclk sample edge rise/fall setup t sis 30 ns mosi input from sclk sample edge transition hold t sih t ck + 25 ns miso output valid after sclk shift edge transition t sov 3t ck + 25 ns ssel inactive t ssh t ck + 25 ns sclk inactive to ssel rising t sd t ck + 25 ns miso output disabled after cs edge rise t slh 2t ck + 50 ns
maxq2000 low-power lcd microcontroller 6 _____________________________________________________________________ ssel sclk ckpol/ckpha 0/1 or 1/0 t mch t mcl mosi msb t moh t mov miso t mis t mih msb-1 msb t mlh msb-1 lsb lsb t mck sclk ckpol/ckpha 0/0 or 1/1 shift sample shift sample spi master timing t sse t sck t sch t sis t sov t slh t sd t ssh t sih t scl shift sample shift sample ssel sclk ckpol/ckpha 0/1 or 1/0 mosi miso sclk ckpol/ckpha 0/0 or 1/1 msb msb msb-1 msb-1 lsb lsb spi slave timing
maxq2000 low-power lcd microcontroller _____________________________________________________________________ 7 digital supply current vs. clock frequency maxq2000 toc01 f hfin (mhz) i dd1 (ma) 10 5 1 2 3 4 5 6 7 8 0 01520 v dd = 2.75v t a = +25 c t a = -40 c t a = 0 c t a = +85 c t ypical operating characteristics pin description pin tqfn qfn name function 40 49 v dd digital supply voltage 22 27 v ddio i/o supply voltage 23, 35 28, 42 gnd ground 45 54 v lcd lcd bias-control voltage. h i g hest lc d d r i ve vol tag e used w i th stati c b i as. c o nnected to an exter nal sour ce. 46 55 v lcd1 lcd bias, voltage 1. lcd drive voltage used with 1/2 and 1/3 lcd bias. an internal resistor- divider sets the voltage. external resistors and capacitors can be used to change the lcd voltage or drive capability at this pin. 47 56 v lcd2 lcd bias, voltage 2. lcd drive voltage used with 1/3 lcd bias. an internal resistor-divider sets the voltage. external resistors and capacitors can be used to change lcd voltage or drive capability at this pin. 48 57 v adj lcd adjustment voltage. connect to an external resistor to provide external control of the lcd contrast. leave disconnected for internal contrast adjustment. 28 33 reset digital, active-low, reset input/output. the cpu is held in reset when this is low and begins executing from the reset vector when released. the pin includes pullup current source and should be driven by an open-drain, external source capable of sinking in excess of 2ma. this pin is driven low as an output when an internal reset condition occurs. 42 51 hfxin high-frequency crystal input. connect an external crystal or resonator between hfxin and hfxout as the high-frequency system clock. alternatively, hfxin is the input for an external, high-frequency clock source when hfxout is floating. 41 50 hfxout high-frequency crystal output/input. connect an external crystal or resonator between hfxin and hfxout as the high-frequency system clock. alternatively, float hfxout when an external, high-frequency clock source is connected to the hfxin pin.
maxq2000 low-power lcd microcontroller 8 _____________________________________________________________________ pin description (continued) pin tqfn qfn name function 29 34 32kin 32khz crystal input. connect an external, 32khz watch crystal between 32kin and 32kout as the low-frequency system clock. alternatively, 32kin is the input for an external, 32khz clock source when 32kout is floating. 30 35 32kout 32khz crystal output/input. connect an external, 32khz watch crystal between 32kin and 32kout as the low-frequency system clock. alternatively, float 32kout when an external, 32khz clock source is connected to the 32kin pin. general-purpose, 8-bit, digital, i/o, type-c port; lcd segment-driver output. these port pins function as both bidirectional i/o pins and lcd segment-drive outputs. all port pins are defaulted as input with weak pullup after a reset. enabling a pin? lcd function disables the general- purpose i/o on the pin. setting the pcf1 bit enables the lcd for all pins on this port and disables the general-purpose i/o function on all pins. 56-pin 68-pin port alternate function 16 6 p1.0 seg8 26 7 p1.1 seg9 36 8 p1.2 seg10 41 p1.3 seg11 52 p1.4 seg12 63 p1.5 seg13 74 p1.6 seg14 1? 66, 67, 68; 1? p1.0?1.7; seg8 seg15 85 p1.7 seg15 general-purpose, 8-bit, digital, i/o, type-c port; lcd segment-driver output. these port pins function as both bidirectional i/o pins and lcd segment-drive outputs. all port pins are defaulted as input with weak pullup after a reset. enabling a pin? lcd function disables the general- purpose i/o on the pin. setting the pcf2 bit enables the lcd for all pins on this port and disables the general-purpose i/o function on all pins. alternate functions 56-pin 68-pin port 56-pin 68-pin ? p2.0 seg16 ? p2.1 seg17 ? p2.2 seg18 ? p2.3 seg19 91 0 p2.4 seg16 seg20 10 11 p2.5 seg17 seg21 11 12 p2.6 seg18 seg22 9?2 6?3 p2.0?2.7; seg16 seg23 12 13 p2.7 seg19 seg23
maxq2000 low-power lcd microcontroller _____________________________________________________________________ 9 pin description (continued) pin tqfn qfn name function g e n e r a l - pu r p o s e , di g it a l , i /o , t y p e - d po r t ; lc d se g m e n t - d r iv e r ou t p u t ; ex t e r n a l ed g e - se l e c t a b le i n t e r r u p t . thi s p or t functi ons as b oth b i d i r ecti onal i/o p i ns and lc d seg m ent- d r i ve outp uts. al l p or t p i ns ar e d efaul ted as i np uts w i th w eak p ul l up s after a r eset. the p or t p ad s ca n b e confi g ur ed as an exter nal i nter r up t for p i ns 7 to 4. if the exter nal i nter r up t i s e nab l ed , the lc d functi on on the associ ated p i n i s d i sab l ed . s etti ng the p c f3 b i t en ab l es the lc d for al l p i ns on thi s p or t and d i sab l es the g ener al - p ur p ose i/o functi on on al l p i ns. it is possible to mix the lcd and interrupt functions on the same port. to do this, the interrupt enable must be established prior to setting the pcf0 bit. care must be taken not to enable the external interrupt while the lcd is in normal operational mode, as this could result in potentially harmful contention between the lcd controller output and the external source connected to the interrupt input. alternate functions 56-pin 68-pin port 56-pin 68-pin ? 4 p3.0 seg24 ? 5 p3.1 seg25 ? 6 p3.2 seg26 ? 7 p3.3 seg27 13 18 p3.4 seg20/int4 seg28/int4 14 19 p3.5 seg21/int5 seg29/int5 15 20 p3.6 seg22/int6 seg30/int6 13?6 14?1 p3.0?3.7; segx; int4?nt7 16 21 p3.7 seg23/int7 seg31/int7 l c d se g m e n t - d r i v e r o u t p u t ; l c d c o m m o n - d r iv e o u t p u t . the sel ecti on of a p i n func ti on as ei ther seg m ent or i ts al ter nati ve com m on- m od e si g nal i s co ntr ol l ed b y the choi ce of d uty cycl e ( d u ty 1:0) . function 56-pin 68-pin 56-pin 68-pin alternate functions 17 22 seg24 seg32 18 23 seg25 seg33 com3 19 24 seg26 seg34 com2 20 25 seg27 seg35 com1 17?1 22?6 segx; com3 com0 21 26 com0 general-purpose, digital, i/o, type-d port; debug port signal; external edge-selectable interrupt. pins default to jtag on por; other functions must be enabled from software. 56-pin 68-pin port alternate functions 24 29 p4.0 tck int8 25 30 p4.1 tdi int9 26 31 p4.2 tms 24?7 29?2 p4.0?4.3; tck/tdi/ tms/tdo; int8, int9 27 32 p4.3 tdo
maxq2000 low-power lcd microcontroller 10 ____________________________________________________________________ pin description (continued) pin tqfn qfn name function ?6 p5.2/rx1/ int10 g e n e r a l - pu r p o s e , di g it a l , i /o , t y p e - d po r t ; se r i a l po r t 1 re c e i v e ; ex t e r n a l ed g e - se l e c t a b le i n t e r r u p t 10 ?7 p5.3/tx1/ int11 g e n e r a l - pu r p o s e , di g it a l , i /o , t y p e - d po r t ; se r i a l po r t 1 tr a n s m i t ; ex t e r n a l ed g e - se l e c t a b l e i n t e r r u p t 11 31 38 p5.4/ ss general-purpose, digital, i/o, type-c port; active-low, spi, slave-select input. becomes the slave-select input in spi mode. 32 39 p5.5; mosi general-purpose, digital, i/o, type-c port; spi, master-out slave-in output. data is clocked out of the microcontroller on sclk? falling edge and into the slave device on sclk? rising edge. becomes miso input in spi mode. 33 40 p5.6; sclk general-purpose, digital, i/o, type-c port; spi, clock output. becomes sclk input in spi mode but limited to sysclk / 8. 34 41 p5.7/miso general-purpose, digital, i/o, type-c port; spi, master-in slave-out input. data is clocked out of the slave on sclk? falling edge and into the microcontroller on sclk? rising edge. becomes mosi output in slave mode. 36 43 p6.0/t1b/ int12 general-purpose, digital, i/o, type-d port; timer 1 alternative output (pwm); external edge- selectable interrupt 12 37 44 p6.1/t1/ int13 g e n e r a l - pu r p o s e , di g it a l , i /o t y p e - d po r t ; t im e r 1 ou t p u t ( pwm ) ; ex t e r n a l ed g e - se le c t a b l e i n t e r r u p t 13 ?5 p6.2/t2b/ ow_out general-purpose, digital, i/o, type-d port; timer 2 alternative output (pwm); 1-wire data output ?6 p6.3/t2/ ow_in general-purpose, digital, i/o, type-d port; timer 2 output (pwm); 1-wire data input 38 47 p6.4/t0b/ wkout0 general-purpose, digital, i/o, type-c port; timer 0 alternative output (pwm); wakeup output 0 39 48 p6.5/t0/ wkout1 general-purpose, digital, i/o, type-c port; timer 0 output (pwm); wakeup output 1 43 52 p7.0/tx0/ int14 g e n e r a l - pu r p o s e , di g it a l , i /o , t y p e - d po r t ; se r i a l po r t 0 tr a n s m i t ; ex t e r n a l, ed g e - se le c t a b l e i n t e r r u p t 14 44 53 p7.1/rx0/ int15 g e n e r a l - pu r p o s e , di g it a l , i /o , t y p e - d po r t ; se r i a l po r t 0 re c e i v e ; ex t e r n a l ed g e - se l e c t a b le i n t e r r u p t 15
maxq2000 low-power lcd microcontroller ____________________________________________________________________ 11 pin description (continued) pin tqfn qfn name function g e n e r a l - pu r p o s e , di g it a l , i /o , t y p e - d po r t ; lc d se g m e n t - d r iv e r ou t p u t ; ex t e r n a l ed g e - se l e c t a b le i n t e r r u p t . thi s p or t func ti ons as b oth b i d i r ecti onal i/o p i ns and lc d seg m ent- d r i ve outp uts. al l p or t p i ns ar e d efaul ted as i np ut w i th w eak p ul l up after a r eset. the p or t p ad s ca n b e confi g ur ed as an exter nal i nter r up t for p i ns 7 to 4. if the exter nal i nter r up t i s e nab l ed , the lc d functi on on the associ ated p i n i s d i sab l ed . s etti ng the p c f0 b i t en ab l es the lc d for al l p i ns on thi s p or t and d i sab l es the g ener al - p ur p ose i/o functi on on al l p i ns. it is possible to mix the lcd and interrupt functions on the same port. to do this, the interrupt enable must be established prior to setting the pcf0 bit. care must be taken not to enable the external interrupt while the lcd is in normal operational mode, as this could result in potentially harmful contention between the lcd controller output and the external source connected to the interrupt input. 56-pin 68-pin port alternate functions 49 58 p0.0 seg0 50 59 p0.1 seg1 51 60 p0.2 seg2 52 61 p0.3 seg3 53 62 p0.4 seg4 int0 54 63 p0.5 seg5 int1 55 64 p0.6 seg6 int2 49?6 58?5 p0.0?0.7; seg0 seg7; int0?nt3 56 65 p0.7 seg7 int3 ep ex p o s e d pa d d le . e xp osed p ad d l e i s on the und er si d e of the p ackag e. it shoul d b e l eft unconnected .
maxq2000 low-power lcd microcontroller 12 ____________________________________________________________________ block diagram sclk mosi miso ss 3/4-wire (spi) interface 32k osc 32kin 32kout rtc and alarms 16-bit risc cpu 32k x 16 (64kbyte) flash rom or mask rom 2k x 8 ram lcd controller/ driver interrupt controller watchdog timer timer0 timer1 timer2 dptr0 dptr1 register file 32kclk 2:1 mux sys_al day_al wdclk sys_al day_al sysclk lcd bias control vlcd1 vlcd2 vadj seg[32]/int16 com[3:1]/seg[33:35] emulation/ download 17 x 8 lcd display ram p4.0/tck/int8 p4.2/tms p4.1/tdi/int9 p4.3/tdo ioint hfxin sclkdiv owout 1wint vlcd v ddio v dd gnd reset wddiv wdclk t2 t2int t1int t0int 3 2:1 muxes tclkdiv t0clk t1clk t2clk t2clk t1clk t0clk u1int 3wint seg[0:3]/p0[0:3] wdint txd0 rxd0 serial uart2 serial uart1 u2int txd1 rxd1 t1 t0 seg[4:7]/p0[4:7]/int[0:3] seg[16:23]/p2[0:7] seg[0]:seg32 seg[8:15]/p1[0:7] gndio hf osc hfxout hfclk com[0] 16 x 16 hw multiply maxq2000 owin gnd seg[24:27]/p3[0:3] seg[28:31]/p3[4:7]/int[4:7] p5.3/tx1/int11 p5.2/rx1/int10 p7.1/rx0/int15 p7.0/tx0/int14 p5.6/sclk p5.7/miso p5.5/mosi p5.4/ss t2b t1b t0b p6.1/t1/int13 p6.0/t1b/int12 p6.5/t0b/wkout p6.4/t0/wkout p6.3/t2/owin p6.2/t2b/owout pad drivers wkout_en wkup wk_out dptr2 1-wire interface v lcd 32khz lcd clk select hf osc / 128 vddio
maxq2000 low-power lcd microcontroller ____________________________________________________________________ 13 detailed description the following is an introduction to the primary features of the microcontroller. more detailed descriptions of the device features can be found in the data sheets, errata sheets, and user? guides described later in the additional documentation section. maxq core architecture the maxq2000 is a low-cost, high-performance, cmos, fully static, 16-bit risc microcontroller with flash memory and an integrated 100- or 132-segment lcd controller. it is structured on a highly advanced, accu- mulator-based, 16-bit risc architecture. fetch and exe- cution operations are completed in one cycle without pipelining, because the instruction contains both the op code and data. the result is a streamlined 20 million instructions-per-second (mips) microcontroller. the highly efficient core is supported by a 16-level hardware stack, enabling fast subroutine calling and task switching. data can be quickly and efficiently manipulated with three internal data pointers. multiple data pointers allow more than one function to access data memory without having to save and restore data pointers each time. the data pointers can automatically increment or decrement following an operation, elimi- nating the need for software intervention. as a result, application speed is greatly increased. instruction set the instruction set is composed of fixed-length, 16-bit instructions that operate on registers and memory loca- tions. the instruction set is highly orthogonal, allowing arithmetic and logical operations to use any register along with the accumulator. special-function registers control the peripherals and are subdivided into register modules. the family architecture is modular, so that new devices and modules can reuse code developed for existing products. the architecture is transport-triggered. this means that writes or reads from certain register locations can also cause side effects to occur. these side effects form the basis for the higher-level op codes defined by the assembler, such as addc, or, jump, etc. the op codes are actually implemented as move instructions between certain register locations, while the assembler handles the encoding, which need not be a concern to the programmer. the 16-bit instruction word is designed for efficient exe- cution. bit 15 indicates the format for the source field of the instruction. bits 0 to 7 of the instruction represent the source for the transfer. depending on the value of the format field, this can either be an immediate value or a source register. if this field represents a register, the lower four bits contain the module specifier and the upper four bits contain the register index in that module. bits 8 to 14 represent the destination for the transfer. this value always represents a destination register, with the lower four bits containing the module specifier and the upper three bits containing the register subindex within that module. any time that it is necessary to directly select one of the upper 24 registers as a desti- nation, the prefix register, pfx, is needed to supply the extra destination bits. this prefix register write is insert- ed automatically by the assembler and requires only one additional execution cycle. memory organization the device incorporates several memory areas: ? 4kwords utility rom, ? 32kwords of flash memory for program storage, ? 1kword of sram for storage of temporary variables, and ? 16-level stack memory for storage of program return addresses and general-purpose use. the memory is arranged by default in a harvard archi- tecture, with separate address spaces for program and data memory. a special mode allows data memory to be mapped into program space, permitting code execution from data memory. in addition, another mode allows pro- gram memory to be mapped into data space, permitting code constants to be accessed as data memory. the incorporation of flash memory allows the devices to be reprogrammed, eliminating the expense of throwing away one-time programmable devices during develop- ment and field upgrades. flash memory can be pass- word protected with a 16-word key, denying access to program memory by unauthorized individuals. a pseudo-von neumann memory map can also be enabled. this places the utility rom, code, and data memory into a single contiguous memory map. this is useful for applications that require dynamic program modification or unique memory configurations. stack memory a 16-bit-wide internal stack provides storage for pro- gram return addresses and general-purpose use. the stack is used automatically by the processor when the call, ret, and reti instructions are executed and interrupts serviced. the stack can also be used explic- itly to store and retrieve data by using the push, pop, and popi instructions.
maxq2000 low-power lcd microcontroller 14 ____________________________________________________________________ 00h 06h 0fh 07h sprs 0000h ffffh ffffh registers 0000h sfrs 1fh ffh 00h 0fh 16 x 16 stack 1k x 16 sram 03ffh 7fffh 8fffh 32k x 16 flash memory 4k x 16 utility rom program memory data memory figure 1. memory map
maxq2000 low-power lcd microcontroller ____________________________________________________________________ 15 on reset, the stack pointer, sp, initializes to the top of the stack (0fh). the call, push, and interrupt-vector- ing operations increment sp, then store a value at the location pointed to by sp. the ret, reti, pop, and popi operations retrieve the value @sp and then decrement sp. utility rom the utility rom is a 4kword block of internal rom memory that defaults to a starting address of 8000h. the utility rom consists of subroutines that can be called from application software. these include: ? in-system programming (bootstrap loader) over jtag or uart interfaces ? in-circuit debug routines ? test routines (internal memory tests, memory loader, etc.) ? user-callable routines for in-application flash pro- gramming and fast table lookup following any reset, execution begins in the utility rom. the rom software determines whether the pro- gram execution should immediately jump to location 0000h, the start of user-application code, or to one of the special routines mentioned. routines within the utili- ty rom are user-accessible and can be called as sub- routines by the application software. more information on the utility rom contents is contained in the maxq family user? guide: maxq2000 supplement . some applications require protection against unautho- rized viewing of program code memory. for these applications, access to in-system programming, in- application programming, or in-circuit debugging func- tions is prohibited until a password has been supplied. the password is defined as the 16 words of physical program memory at addresses x0010h to x001fh. a single password lock (pwl) bit is implemented in the sc register. when the pwl is set to one (power-on reset default), the password is required to access the utility rom, including in-circuit debug and in-system programming routines that allow reading or writing of internal memory. when pwl is cleared to zero, these utilities are fully accessible without password. the password is automatically set to all ones following a mass erase. programming the flash memory of the microcontroller can be pro- grammed by two different methods: in-system pro- gramming and in-application programming. both methods afford great flexibility in system design as well as reduce the life-cycle cost of the embedded system. these features can be password protected to prevent unauthorized access to code memory. in-system programming an internal bootstrap loader allows the device to be reloaded over a simple jtag interface. as a result, software can be upgraded in-system, eliminating the need for a costly hardware retrofit when updates are required. remote software uploads are possible that enable physically inaccessible applications to be fre- quently updated. the interface hardware can be a jtag connection to another microcontroller, or a con- nection to a pc serial port using a serial-to-jtag con- verter such as the maxqjtag-001, available from maxim integrated products. if in-system programmabili- ty is not required, a commercial gang programmer can be used for mass programming. activating the jtag interface and loading the test access port (tap) with the system programming instruc- tion invokes the bootstrap loader. setting the spe bit to 1 during reset through the jtag interface executes the bootstrap-loader-mode program that resides in the utility rom. when programming is complete, the bootstrap loader can clear the spe bit and reset the device, allow- ing the device to bypass the utility rom and begin exe- cution of the application software. the following bootstrap loader functions are supported: ? load ? dump ? crc ? verify ? erase optionally, the bootstrap loader can be invoked by the application code. in this mode, the application software would configure the spe and pss bits for uart com- munication, then jump to the start of the utility rom. in this way, the bootstrap loader can be accessed through another uart-enabled peripheral, or a pc serial port through an rs-232 transceiver such as the max232. because the bootstrap loader defaults to the jtag con- figuration on reset, the uart versus jtag selection must be made from the application code. as a result, bootstrap loader access through the uart is not possi- ble in an unprogrammed device.
maxq2000 low-power lcd microcontroller 16 ____________________________________________________________________ in-application programming the in-application programming feature allows the microcontroller to modify its own flash program memory while simultaneously executing its application software. this allows on-the-fly software updates in mission- critical applications that cannot afford downtime. alternatively, it allows the application to develop cus- tom loader software that can operate under the control of the application software. the utility rom contains user-accessible flash programming functions that erase and program flash memory. these functions are described in detail in the user? guide supplement for this device. register set most functions of the device are controlled by sets of reg- isters. these registers provide a working space for mem- ory operations as well as configuring and addressing peripheral registers on the device. registers are divided into two major types: system registers and peripheral reg- isters. the common register set, also known as the sys- tem registers, includes the alu, accumulator registers, data pointers, interrupt vectors and control, and stack pointer. the peripheral registers define additional func- tionality that may be included by different products based on the maxq architecture. this functionality is broken up into discrete modules so that only the features required for a given product need to be included. tables 1 and 4 show the maxq2000 register set. table 1. system register map module name (base specifier) register index ap (8h) a (9h) pfx (bh) ip (ch) sp (dh) dpc (eh) dp (fh) 0xh ap a[0] pfx ip 1xh apc a[1] sp 2xh a[2] iv 3xh a[3] offs dp0 4xh psf a[4] dpc 5xh ic a[5] gr 6xh imr a[6] lc0 grl 7xh a[7] lc1 bp dp1 8xh sc a[8] grs 9xh a[9] grh axh a[10] grxl bxh iir a[11] fp cxh a[12] dxh a[13] exh ckcn a[14] fxh wdcn a[15] note: names that appear in italics indicate that all bits of a register are read-only. names that appear in bold indicate that a regi ster is 16 bits wide. registers in module ap are bit addressable.
maxq2000 low-power lcd microcontroller ____________________________________________________________________ 17 table 2. system register bit functions register bit register 15 14 13 12 11 10 987654321 0 ap ap (4 bits) apc clr ids mod2 mod1 mod0 psf zs gpf1 gpf0 ov c e ic cgds ins ige imr ims im4 im3 im2 im1 im0 sc tap cda0 rod pwl iir iis ii4 ii3 ii2 ii1 ii0 ckcn rgsl rgmd stop swb pmme cd1 cd0 wdcn por ewdi wd1 wd0 wdif wtrf ewt rwt a[n] (0..15) a[n] (16 bits) pfx pfx (16 bits) ip ip (16 bits) sp sp (4 bits) iv iv (16 bits) lc[0] lc[0] (16 bits) lc[1] lc[1] (16 bits) offs offs (8 bits) dpc wbs2 wbs1 wbs0 sdps1 sdps0 gr gr.15 gr.14 gr.13 gr.12 gr.11 gr.10 gr.9 gr.8 gr.7 gr.6 gr.5 gr.4 gr.3 gr.2 gr.1 gr.0 grl gr.7 gr.6 gr.5 gr.4 gr.3 gr.2 gr.1 gr.0 bp bp (16 bits) grs gr.7 gr.6 gr.5 gr.4 gr.3 gr.2 gr.1 gr.0 gr.15 gr.14 gr.13 gr.12 gr.11 gr.10 gr.9 gr.8 grh gr.15 gr.14 gr.13 gr.12 gr.11 gr.10 gr.9 gr.8 grxl gr.7 gr.7 gr.7 gr.7 gr.7 gr.7 gr.7 gr.7 gr.7 gr.6 gr.5 gr.4 gr.3 gr.2 gr.1 gr.0 fp fp (16 bits) dp[0] dp[0] (16 bits) dp[1] dp[1] (16 bits)
maxq2000 low-power lcd microcontroller 18 ____________________________________________________________________ table 3. system register bit reset values register bit register 15 14 13 12 11 10 9876543210 ap 00000000 apc 00000000 psf 10000000 ic 00000000 imr 00000000 sc 000000s0 iir 00000000 ckcn 0s s0 0000 wdcn ss 000000 a[n] (0..15) 0000000000000000 pfx 0000000000000000 ip 1000000000000000 sp 0000000000001111 iv 0000000000000000 lc[0] 0000000000000000 lc[1] 0000000000000000 offs 00000000 dp c 0000000000011100 gr 0000000000000000 grl 00000000 bp 0000000000000000 gr s 0000000000000000 grh 00000000 grxl 0000000000000000 fp 0000000000000000 dp0 0000000000000000 dp1 0000000000000000
maxq2000 low-power lcd microcontroller ____________________________________________________________________ 19 table 4. peripheral register map module name (base specifier) register index m0 (x0h) m1 (x1h) m2 (x2h) m3 (x3h) m4 (x4h) m5 (x5h) 0xh po0 po4 mcnt t2cna0 t2cna1 1xh po1 po5 ma t2h0 t2h1 2xh po2 po6 mb t2rh0 t2rh1 3xh po3 po7 mc2 t2ch0 t2ch1 4xh mc1 t2cna2 5xh mc0 spib t2h2 6xh eif0 eif1 scon0 scon1 t2rh2 7xh eie0 eie1 sbuf0 sbuf1 t2ch2 8xh pi0 pi4 smd0 smd1 t2cnb1 9xh pi1 pi5 pr0 pr1 t2v1 axh pi2 pi6 t2r1 bxh pi3 pi7 mc1r t2c1 cxh eies0 eies1 mc0r t2cnb0 t2cnb2 dxh lcra t2v0 t2v2 exh lcfg t2r0 t2r2 fxh lcd16 t2c0 t2c2 10xh pd0 pd4 lcd0 t2cfg0 t2cfg1 11xh pd1 pd5 lcd1 t2cfg2 12xh pd2 pd6 lcd2 13xh pd3 pd7 lcd3 owa 14xh lcd4 owd 15xh lcd5 spicn 16xh lcd6 spicf 17xh lcd7 spick 18xh lcd8 icdt0 19xh rcnt lcd9 icdt1 1axh rtss lcd10 icdc 1bxh rtsh lcd11 icdf 1cxh rtsl lcd12 icdb 1dxh rssa lcd13 icda 1exh rash svs lcd14 icdd 1fxh rasl wko lcd15 tm note: names that appear in italics indicate that all bits of a register are read-only. names that appear in bold indicate that a regi ster is 16 bits wide.
maxq2000 low-power lcd microcontroller 20 ____________________________________________________________________ table 5. peripheral register bit functions register bit register 15 14 13 12 11 10 98 76543210 po0 po0 (8 bits) po1 po1 (8 bits) po2 po2 (8 bits) po3 po3 (8 bits) eif0 ie7 ie6 ie5 ie4 ie3 ie2 ie1 ie0 eie0 ex7 ex6 ex5 ex4 ex3 ex2 ex1 ex0 pi0 pi0 (8 bits) pi1 pi1 (8 bits) pi2 pi2 (8 bits) pi3 pi3 (8 bits) eies0 it7 it6 it5 it4 it3 it2 it1 it0 pd0 pd0 (8 bits) pd1 pd1 (8 bits) pd2 pd2 (8 bits) pd3 pd3 (8 bits) rcnt we x32d acs alsf aldf rdye rdy busy ase ade rtce rtss rtss (8 bits) rtsh rtsh (16 bits) rtsl rtsl (16 bits) rssa rssa (8 bits) rash rash (8 bits) rasl rasl (16 bits) po4 po4 (5 bits) po5 po5 (8 bits) po6 po6 (8 bits) po7 po7 (2 bits) eif1 ie15 ie14 ie13 ie12 ie11 ie10 ie9 ie8 eie1 ex15 ex14 ex13 ex12 ex11 ex10 ex9 ex8 pi4 pi4 (5 bits) pi5 pi5 (8 bits) pi6 pi6 (8 bits) pi7 pi7 (2 bits) eies1 it15 it14 it13 it12 it11 it10 it9 it8 pd4 pd4 (5 bits) pd5 pd5 (8 bits) pd6 pd6 (8 bits)
maxq2000 low-power lcd microcontroller ____________________________________________________________________ 21 table 5. peripheral register bit functions (continued) register bit register 15 14 13 12 11 10 98 76543210 pd7 pd7 (2 bits) svs sv67 sv66 sv65 sv64 sv71 sv70 wko wkl wke1 wke0 mcnt of mcw cld squ opcs msub mmac sus ma ma (16 bits) mb mb (16 bits) mc2 mc2 (16 bits) mc1 mc1 (16 bits) mc0 mc0 (16 bits) scon0 sm0/fe sm1 sm2 ren tb8 rb8 ti ri sbuf0 sbuf0 (8 bits) smd0 esi0 smod0 fede0 pr0 pr0 (16 bits) mc1r mc1r (16 bits) mc0r mc0r (16 bits) lcra duty1 duty0 frm3 frm2 frm1 frm0 lccs lrig lra4 lra3 lra2 lra1 lra0 lcfg pcf3 pcf2 pcf1 pcf0 opm dpe lcd[0..15] lcd[0..15] (8 bits) t2cna0 et2 t2oe0 t2pol0 tr2l tr2 cprl2 ss2 g2en t2h0 t2v0.15 t2v0.14 t2v0.13 t2v0.12 t2v0.11 t2v0.10 t2v0.9 t2v0.8 t2rh0 t2r0.15 t2r0.14 t2r0.13 t2r0.12 t2r0.11 t2r0.10 t2r0.9 t2r0.8 t2ch0 t2c0.15 t2c0.14 t2c0.13 t2c0.12 t2c0.11 t2c0.10 t2c0.9 t2c0.8 spib spib (16 bits) scon1 sm0/fe sm1 sm2 ren tb8 rb8 ti ri sbuf1 sbuf1 (8 bits) smd1 esi1 smod1 fede1 pr1 pr1 (16 bits) t2cnb0 et2l t2oe1 t2pol1 tr2l tf2 tf2l tcc2 tc2l t2v0 t2v0.15 t2v0.14 t2v0.13 t2v0.12 t2v0.11 t2v0.10 t2v0.9 t2v0.8 t2v0.7 t2v0.6 t2v0.5 t2v0.4 t2v0.3 t2v0.2 t2v0.1 t2v0.0 t2r0 t2r0.15 t2r0.14 t2r0.13 t2r0.12 t2r0.11 t2r0.10 t2r0.9 t2r0.8 t2r0.7 t2r0.6 t2r0.5 t2r0.4 t2r0.3 t2r0.2 t2r0.1 t2r0.0 t2c0 t2c0.15 t2c0.14 t2c0.13 t2c0.12 t2c0.11 t2c0.10 t2c0.9 t2c0.8 t2c0.7 t2c0.6 t2c0.5 t2c0.4 t2c0.3 t2c0.2 t2c0.1 t2c0.0 t2cfg0 t2ci div2 div1 div0 t2md ccf1 ccf0 c/t2 owa a2a1a0 owd owd (8 bits) spicn stby spic rovr wcol modf modfe mstm spien
maxq2000 low-power lcd microcontroller 22 ____________________________________________________________________ table 5. peripheral register bit functions (continued) register bit register 15 14 13 12 11 10 98 76543210 spicf espi1 chr ckpha ckpol spick ckr7 ckr6 ckr5 ckr4 ckr3 ckr2 ckr1 ckr0 icdc dme rege cmd3 cmd2 cmd1 cmd0 icdf pss1 pss0 spe txc icdb icdb (8 bits) icda icda (16 bits) icdd icdd (16 bits) t2cna1 et2 t2oe0 t2pol0 tr2l tr2 cprl2 ss2 g2en t2h1 t2v1.15 t2v1.14 t2v1.13 t2v1.12 t2v1.11 t2v1.10 t2v1.9 t2v1.8 t2rh1 t2r1.15 t2r1.14 t2r1.13 t2r1.12 t2r1.11 t2r1.10 t2r1.9 t2r1.8 t2ch1 t2c1.15 t2c1.14 t2c1.13 t2c1.12 t2c1.11 t2c1.10 t2c1.9 t2c1.8 t2cna2 et2 t2oe0 t2pol0 tr2l tr2 cprl2 ss2 g2en t2h2 t2v2.15 t2v2.14 t2v2.13 t2v2.12 t2v2.11 t2v2.10 t2v2.9 t2v2.8 t2rh2 t2r2.15 t2r2.14 t2r2.13 t2r2.12 t2r2.11 t2r2.10 t2r2.9 t2r2.8 t2ch2 t2c2.15 t2c2.14 t2c2.13 t2c2.12 t2c2.11 t2c2.10 t2c2.9 t2c2.8 t2cnb1 et2l t2oe1 t2pol1 tr2l tf2 tf2l tcc2 tc2l t2v1 t2v1.15 t2v1.14 t2v1.13 t2v1.12 t2v1.11 t2v1.10 t2v1.9 t2v1.8 t2v1.7 t2v1.6 t2v1.5 t2v1.4 t2v1.3 t2v1.2 t2v1.1 t2v1.0 t2r1 t2r1.15 t2r1.14 t2r1.13 t2r1.12 t2r1.11 t2r1.10 t2r1.9 t2r1.8 t2r1.7 t2r1.6 t2r1.5 t2r1.4 t2r1.3 t2r1.2 t2r1.1 t2r1.0 t2c1 t2c1.15 t2c1.14 t2c1.13 t2c1.12 t2c1.11 t2c1.10 t2c1.9 t2c1.8 t2c1.7 t2c1.6 t2c1.5 t2c1.4 t2c1.3 t2c1.2 t2c1.1 t2c1.0 t2cnb2 et2l t2oe1 t2pol1 tr2l tf2 tf2l tcc2 tc2l t2v2 t2v2.15 t2v2.14 t2v2.13 t2v2.12 t2v2.11 t2v2.10 t2v2.9 t2v2.8 t2v2.7 t2v2.6 t2v2.5 t2v2.4 t2v2.3 t2v2.2 t2v2.1 t2v2.0 t2r2 t2r2.15 t2r2.14 t2r2.13 t2r2.12 t2r2.11 t2r2.10 t2r2.9 t2r2.8 t2r2.7 t2r2.6 t2r2.5 t2r2.4 t2r2.3 t2r2.2 t2r2.1 t2r2.0 t2c2 t2c2.15 t2c2.14 t2c2.13 t2c2.12 t2c2.11 t2c2.10 t2c2.9 t2c2.8 t2c2.7 t2c2.6 t2c2.5 t2c2.4 t2c2.3 t2c2.2 t2c2.1 t2c2.0 t2cfg1 t2ci div2 div1 div0 t2md ccf1 ccf0 c/t2 t2cfg2 t2ci div2 div1 div0 t2md ccf1 ccf0 c/t2
maxq2000 low-power lcd microcontroller ____________________________________________________________________ 23 register bit register 15 14 13 12 11 10 9876543210 po0 1 1111111 po1 1 1111111 po2 1 1111111 po3 1 1111111 eif0 0 0000000 eie0 0 0000000 pi0 s sssssss pi1 s sssssss pi2 s sssssss pi3 s sssssss eies0 0 0000000 pd0 0 0000000 pd1 0 0000000 pd2 0 0000000 pd3 0 0000000 rcnt 0 s s 0 0 0 0 0 s s 0 0 1 s s s rtss s sssssss rtsh s s s s s s s s s s s s s s s s rtsl s s s s s s s s s s s s s s s s rssa 0 0000000 rash 0 0000000 rasl 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 po4 0 0011111 po5 1 1111111 po6 1 1111111 po7 0 0000011 eif1 0 0000000 eie1 0 0000000 pi4 000sssss pi5 s sssssss pi6 s sssssss pi7 0 00000ss eies1 0 0000000 pd4 0 0000000 pd5 0 0000000 pd6 0 0000000 pd7 0 0000000 svs 0 0000000 wko 0 0000000 table 6. peripheral register reset values
maxq2000 low-power lcd microcontroller 24 ____________________________________________________________________ table 6. peripheral register reset values (continued) register bit register 15 14 13 12 11 10 987 6543210 mcnt 0 0000000 ma 0000000000000000 mb 0000000000000000 mc2 0 0 0 0000000000000 mc1 0 0 0 0000000000000 mc0 0 0 0 0000000000000 scon0 0 0000000 sbuf0 0 0000000 smd0 0 0000000 pr0 0 0 0 0000000000000 mc1r 0 0 0 0000000000000 mc0r 0 0 0 0000000000000 lcra 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 lcfg 0 0000000 lcd[0..15] 0 0000000 t2cna0 0 0000000 t2h0 0 0000000 t2rh0 0 0000000 t2ch0 0 0000000 spib 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 scon1 0 0000000 sbuf1 0 0000000 smd1 0 0000000 pr1 0 0 0 0000000000000 t2cnb0 0 0 0 0 0 0 0 0 t2v0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 t2r0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 t2c0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 t2cfg0 0 0000000 owa 0 0000000 owd 0 0000000 spicn 0 0000000 spicf 0 0000000 spick 0 0000000 icdc s sssssss icdf s sssssss icdb s sssssss icda s s s s s s s s s s s s s s s s icdd s s s s s s s s s s s s s s s s t2cna1 0 0000000
maxq2000 low-power lcd microcontroller ____________________________________________________________________ 25 register bit register 15 14 13 12 11 10 9876543210 t2h1 0 0000000 t2rh1 0 0000000 t2ch1 0 0000000 t2cna2 0 0000000 t2h2 0 0000000 t2rh2 0 0000000 t2ch2 0 0000000 t2cnb1 0 0000000 t2v1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 t2r1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 t2c1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 t2cnb2 0 0000000 t2v2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 t2r2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 t2c2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 t2cfg1 0 0000000 t2cfg2 0 0000000 table 6. peripheral register reset values (continued)
maxq2000 low-power lcd microcontroller 26 ____________________________________________________________________ maxq2000 glitch-free mux glitch-free mux div 1 div 2 div 4 div 8 32khz pwm clock divider selector w ake-up alarm timers default ring select wa tchdog timer reset dog rwt reset power-on reset stop stop power-on reset swb interrupt/serial port reset stop rgsl xdog done rgmd power-on reset wa tchdog reset clock generation system clock enable wa tchdog interrupt ring enable 32khz crystal crystal monitor enable input hf crystal crystal kll xdog startup timer clk input reset xdog count xdog done figure 2. clock sources system timing for maximum versatility, the maxq2000 generates its internal system clock from one of five possible sources: ? internal ring oscillator ? external high-frequency crystal or ceramic resonator, using an internal oscillator ? external high-frequency clock source ? external 32khz crystal or ceramic resonator, using an internal oscillator ? external 32khz clock source a crystal warmup counter enhances operational relia- bility. each time the external crystal oscillation must restart, such as after exiting stop mode, the device initi- ates a crystal warmup period of 65,536 oscillations. this allows time for the crystal amplitude and frequency to stabilize before using it as a clock source. while in the warmup mode, the device can begin operation from the internal ring oscillator and automatically switch back to the crystal as soon as it is ready.
maxq2000 low-power lcd microcontroller ____________________________________________________________________ 27 power management advanced power-management features minimize power consumption by dynamically matching the pro- cessing speed of the device to the required perfor- mance level. this means device operation can be slowed and power consumption minimized during peri- ods of reduced activity. when more processing power is required, the microcontroller can increase its operat- ing frequency. software-selectable clock-divide opera- tions allow flexibility, selecting whether a system clock cycle is 1, 2, 4, or 8 oscillator cycles. by performing this function in software, a lower power state can be entered without the cost of additional hardware. for extremely power-sensitive applications, three addi- tional low-power modes are available: ? pmm1: divide-by-256 power-management mode (pmme = 1, cd1:0 = 00b) ? pmm2: 32khz power-management mode (pmme = 1, cd1:0 = 11b) ? stop mode (stop = 1) in pmm1, one system clock is 256 oscillator cycles, sig- nificantly reducing power consumption while the micro- controller functions at reduced speed. in pmm2, the device can run even slower by using the 32khz oscilla- tor as the clock source. the optional switchback fea- ture allows enabled interrupt sources including external interrupts, uarts, and the spi module to quickly exit the power-management modes and return to a faster internal clock rate. power consumption reaches its minimum in stop mode. in this mode, the external oscillator, system clock, and all processing activity is halted. stop mode is exited when an enabled external interrupt pin is triggered, an external reset signal is applied to the reset pin, or the rtc time- of-day alarm is activated. upon exiting stop mode, the microcontroller can choose to wait for the external high- frequency crystal to complete its warmup period, or it can start execution immediately from its internal ring oscillator while the warmup period completes. interrupts multiple reset sources are available for quick response to internal and external events. the maxq architecture uses a single interrupt vector (iv), single interrupt-ser- vice routine (isr) design. for maximum flexibility, inter- rupts can be enabled globally, individually, or by module. when an interrupt condition occurs, its individ- ual flag is set, even if the interrupt source is disabled at the local, module, or global level. interrupt flags must be cleared within the user-interrupt routine to avoid repeated interrupts from the same source. application software must ensure a delay between the write to the flag and the reti instruction to allow time for the inter- rupt hardware to remove the internal interrupt condition. asynchronous interrupt flags require a one-instruction delay and synchronous interrupt flags require a two- instruction delay. when an enabled interrupt is detected, software jumps to a user-programmable interrupt vector location. the iv register defaults to 0000h on reset or power-up, so if it is not changed to a different address, the user pro- gram must determine whether a jump to 0000h came from a reset or interrupt source. once software control has been transferred to the isr, the interrupt identification register (iir) can be used to determine if a system register or peripheral register was the source of the interrupt. the specified module can then be interrogated for the specific interrupt source and software can take appropriate action. because the interrupts are evaluated by user software, the user can define a unique interrupt priority scheme for each application. the following interrupt sources are available. sources marked with an asterisk are not available on the 56-pin version. ? watchdog interrupt ? external interrupts 0 to 15 (int10*, int11*) ? rtc time-of-day and subsecond alarms ? serial port 0 receive and transmit interrupts ? serial port 1 receive and transmit interrupts* ? spi mode fault, write collision, receive overrun, and transfer complete interrupts ? timer 0 low compare, low overflow, capture/compare, and overflow interrupts ? timer 1 low compare, low overflow, capture/compare, and overflow interrupts ? timer 2 low compare, low overflow, capture/compare, and overflow interrupts ? 1-wire presence detect, transmit buffer empty, transmit shift register empty, receive buffer full, and shift register full, short, and low interrupts* reset sources several reset sources are provided for microcontroller control. although code execution is halted in the reset state, the high-frequency oscillator and the ring oscillator continue to oscillate. internal resets such as the power- on and watchdog resets assert the reset pin low.
maxq2000 low-power lcd microcontroller 28 ____________________________________________________________________ power-on reset an internal power-on reset circuit enhances system reli- ability. this circuit forces the device to perform a power-on reset whenever a rising voltage on v ddio climbs above approximately 1.8v. at this point the fol- lowing events occur: ? all registers and circuits enter their reset state ? the por flag (wdcn.7) is set to indicate the source of the reset ? the ring oscillator becomes the clock source and ? code execution begins at location 8000h watchdog timer reset the watchdog timer functions are described in the maxq family user? guide . execution resumes at loca- tion 8000h following a watchdog timer reset. external system reset asserting the external reset pin low causes the device to enter the reset state. the external reset functions as described in the maxq family user? guide . execution resumes at location 8000h after the reset pin is released. i/o ports the microcontroller uses the type c and type d bidirec- tional i/o ports described in the maxq family user? guide . the use of three port types allows for maximum flexibility when interfacing to external peripherals. each port has eight independent, general-purpose i/o pins and three configure/control registers. many pins support alternate functions such as timers or interrupts, which are enabled, controlled, and monitored by dedicated periph- eral registers. using the alternate function automatically converts the pin to that function. type-c port pins have schmitt trigger receivers and full cmos output drivers, and can support alternate functions. the pin is either tri-stated or weak pullup when defined as an input, dependent on the state of the corresponding bit in the output register. type-d port pins have schmitt trigger receivers and full cmos output drivers, and can support alternate functions. the pin is either tri-stated or weak pullup when defined as an input, dependent on the state of the corresponding bit in the output register. all type-d pins also have interrupt capability. maxq2000 pd.x sf direction sf enable mux mux po.x v ddio sf output v ddio weak i/o pad pin.x interrupt flag flag pi.x or sf input eies.x type-d port only detect circuit figure 3. type-c/d port pin schematic
maxq2000 low-power lcd microcontroller ____________________________________________________________________ 29 high-speed hardware multiplier the hardware multiplier module performs high-speed multiply, square, and accumulate operations, and can complete a 16-bit x 16-bit multiply-and-accumulate operation in a single cycle. the hardware multiplier consists of two 16-bit parallel-load operand registers (ma, mb), an accumulator that is formed by up to three 16-bit parallel registers (mc2, mc1, and mc0), and a status/control register (mcnt). loading the registers can automatically initiate the operation, saving time on repetitive calculations. the accumulate function of the hardware multiplier is an essential element of digital fil- tering, signal processing, and pid control systems. the hardware multiplier module supports the following operations: ? multiply unsigned (16 bit x 16 bit) ? multiply signed (16 bit x 16 bit) ? multiply-accumulate unsigned (16 bit x 16 bit) ? multiply-accumulate signed (16 bit x 16 bit) ? square unsigned (16 bit) ? square signed (16 bit) ? square-accumulate unsigned (16 bit) ? square-accumulate signed (16 bit) real-time clock a binary real-time clock keeps the time of day in absolute seconds with 1/256-second resolution. the 32-bit second counter can count up to approximately 136 years and be translated to calendar format by the application software. a time-of-day alarm and indepen- dent subsecond alarm can cause an interrupt, or wake the device from stop mode. the independent subsecond alarm runs from the same rtc, and allows the application to perform periodic interrupts up to ones with a granularity of approximately 3.9ms. this creates an additional timer that can be used to measure long periods without performance degradations. traditionally, long time periods have been measured using multiple interrupts from shorter programmable timers. each timer interrupt required servicing, with each accompanying interruption slowing system operation. by using the rtc subsecond timer as a long-period timer, only one interrupt is needed, eliminating the performance hit associated with using a shorter timer. an internal crystal oscillator clocks the rtc using inte- grated 6pf load capacitors, and give the best perfor- mance when mated with a 32.768khz crystal rated for a 6pf load. no external load capacitors are required. higher accuracy can be obtained by supplying an exter- nal clock source to the rtc. the frequency accuracy of a crystal-based oscillator circuit is dependent upon crys- tal accuracy, the match between the crystal and the oscillator capacitor load, ambient temperature, etc. an error of 20ppm is equivalent to approximately 1 minute per month. programmable timers the microcontroller incorporates three 16-bit program- mable instances of the timer 2 peripheral, denoted tr2a, tr2b, and tr2c. these timers can be used in counter/timer/capture/compare/pwm functions, allow- ing precise control of internal and external events. timer 2 supports optional single-shot, external gating, and polarity control options. timer 2 the timer 2 peripheral includes the following: ? 16-bit autoreload timer/counter ? 16-bit capture ? 16-bit counter ? 8-bit capture and 8-bit timer ? 8-bit counter and 8-bit timer w atchdog timer an internal watchdog timer greatly increases system reliability. the timer resets the device if software execu- tion is disturbed. the watchdog timer is a free-running counter designed to be periodically reset by the appli- cation software. if software is operating correctly, the counter will be periodically reset and never reach its maximum count. however, if software operation is inter- rupted, the timer does not reset, triggering a system reset and optionally a watchdog timer interrupt. this protects the system against electrical noise or electro- static discharge (esd) upsets that could cause uncon- trolled processor operation. the internal watchdog timer is an upgrade to older designs with external watchdog devices, reducing system cost and simulta- neously increasing reliability.
maxq2000 low-power lcd microcontroller 30 ____________________________________________________________________ the watchdog timer is controlled through bits in the wdcn register. its timeout period can be set to one of four programmable intervals ranging from 2 12 to 2 21 system clocks in its default mode, allowing flexibility to support different types of applications. the interrupt occurs 512 system clocks before the reset, allowing the system to execute an interrupt and place the system in a known, safe state before the device performs a total system reset. at 16mhz, watchdog timeout periods can be programmed from 256? to 33.5s, depending on the system clock mode. serial peripherals the microcontroller incorporates several common seri- al-peripheral interfaces for interconnection with popular external devices. multiple formats provide maximum flexibility and lower cost when designing a system. uarts serial interfacing is provided through one (-rbx) or two (-rax) 8051-style universal synchronous/asynchronous receiver/transmitters. the uart allows the device to conveniently communicate with other rs-232 interface- enabled devices, as well as pcs and serial modems when paired with an external rs-232 line driver/receiv- er. the dual independent uarts can communicate simultaneously at different baud rates with two separate peripherals. the uart can detect framing errors and indicate the condition through a user-accessible soft- ware bit. the time base of the serial ports is derived from either a division of the system clock or the dedicated baud clock generator. the following table summarizes the operating characteristics as well as the maximum baud rate of each mode: 1-wire bus master the MAXQ2000-RAX includes a dallas semiconductor 1-wire bus master, which communicates to other 1-wire peripherals, including i button products, through a simple bidirectional signaling scheme over a single electrical connection. the bus master provides com- plete control of the 1-wire bus and transmit and receive activities, and generates all timing and control sequences of the 1-wire bus. communication between the cpu and the bus master is achieved through read/write access of the 1-wire master address (owa) and 1-wire master data (owd) peripheral registers. detailed operation of the 1-wire bus is described in the book of i button standards (www.maxim-ic.com/ ibuttonbook ). serial-peripheral interface (spi) module the spi port is a common, high-speed, synchronous peripheral interface that shifts a bit stream of variable length and data rate between the microcontroller and other peripheral devices. the spi can be used to com- municate with other microcontrollers, serial shift regis- ters, or display drivers. multiple master and slave modes permit communication with multiple devices in the same system. programmable clock frequency, character lengths, polarity, and error handling enhance the usefulness of the peripheral. the maximum baud rate of the spi interface is 1/2 the system clock for mas- ter mode operation and 1/8 the system clock for slave mode operation. mode type start bits data bits stop bit max baud rate at 16mhz mode 0 synchronous n/a 8 n/a 4mbps mode 1 asynchronous 1 8 1 500kbps mode 2 asynchronous 1 8 + 1 1 500kbps mode 3 asynchronous 1 8 + 1 1 500kbps i button is a registered trademark of dallas semiconductor corp.
maxq2000 low-power lcd microcontroller ____________________________________________________________________ 31 in-circuit debug embedded debugging capability is available through the jtag-compatible test access port. embedded debug hardware and embedded rom firmware pro- vide in-circuit debugging capability to the user applica- tion, eliminating the need for an expensive in-circuit emulator. figure 4 shows a block diagram of the in-cir- cuit debugger. the in-circuit debug features include: ? a hardware debug engine, ? a set of registers able to set breakpoints on register, code, or data accesses, and ? a set of debug service routines stored in the utility rom. the embedded hardware debug engine is an indepen- dent hardware block in the microcontroller. the debug engine can monitor internal activities and interact with selected internal registers while the cpu is executing user code. collectively, the hardware and software fea- tures allow two basic modes of in-circuit debugging: ? background mode allows the host to configure and set up the in-circuit debugger while the cpu continues to execute the application software at full speed. debug mode can be invoked from background mode. ? debug mode allows the debug engine to take control of the cpu, providing read/write access to internal reg- isters and memory, and single-step trace operation. lcd controller the maxq2000 microcontroller incorporates an lcd controller that interfaces to common low-voltage dis- plays. by incorporating the lcd controller into the microcontroller, the design requires only an lcd glass rather than a considerably more expensive lcd mod- ule. every character in an lcd glass is composed of one or more segments, each of which is activated by selecting the appropriate segment and common signal. the microcontroller can multiplex combinations of up to 33 segment (seg0?eg32) outputs and four common signal outputs (com0?om3). unused segment out- puts can be used as general-purpose port pins. the segments are easily addressed by writing to dedi- cated display memory. once the lcd controller set- tings and display memory have been initialized, the 17-byte display memory is periodically scanned, and the segment and common signals are generated auto- matically at the selected display frequency. no addi- tional processor overhead is required while the lcd controller is running. unused display memory can be used for general-purpose storage. the design is further simplified and cost-reduced by the inclusion of software-adjustable internal voltage dividers to control display contrast, using either v ddio or an external voltage. if desired, contrast can also be controlled with an external resistance. the features of the lcd controller include the following: ? automatic lcd segment and common-drive signal generation ? four display modes supported: static (com0) 1/2 duty multiplexed with 1/2 bias voltages (com0, com1) 1/3 duty multiplexed with 1/3 bias voltages (com0, com1, com2) 1/4 duty multiplexed with 1/3 bias voltages (com0, com1, com2, com3) ? up to 36 segment outputs and four common-signal outputs ? 17 bytes (136 bits) of display memory ? flexible lcd clock source, selectable from 32khz or hfclk / 128 ? adjustable frame frequency ? internal voltage-divider resistors eliminate require- ment for external components ? internal adjustable resistor allows contrast adjustment without external components tap controller cpu debug engine debug service routines (utility rom) tms tck tdi tdo control breakpoint address d ata maxq2000 figure 4. in-circuit debugger
maxq2000 low-power lcd microcontroller 32 ____________________________________________________________________ ? flexibility to use external resistors to adjust drive volt- ages and current capacity a simple lcd-segmented glass interface example demonstrates the minimal hardware required to inter- face to a maxq2000 microcontroller. a two-character lcd is controlled, with each character containing seven segments plus decimal point. the lcd controller is configured for 1/2 duty cycle operation, meaning the active segment is controlled using a combination of segment signals, and com0 or com1 signals are used to select the active display. applications the low-power, high-performance risc architecture of the maxq2000 makes it an excellent fit for many portable or battery-powered applications that require cost-effective computing. the high-throughput core is complemented by a 16-bit hardware multiplier-accumu- lator, allowing the implementation of sophisticated com- putational algorithms. applications benefit from a wide range of peripheral interfaces, allowing the microcon- troller to communicate with many external devices. with integrated lcd support of up to 100 or 132 segments, applications can support complex user interfaces. displays are driven directly with no additional external hardware required. contrast can be adjusted using a built-in, adjustable resistor. the simplified architecture reduces component count and board space, critical factors in the design of portable systems. the maxq2000 is ideally suited for applications such as medical instrumentation, portable blood glucose equipment, and data collection devices. for blood glu- cose measurement, the microcontroller integrates an spi interface that directly connects with analog front ends for measuring test strips. additional documentation designers must have four documents to fully use all the features of this device. this data sheet contains pin descriptions, feature overviews, and electrical specifi- cations. errata sheets contain deviations from pub- lished specifications. the user? guides offer detailed information about device features and operation. the following documents can be downloaded from www.maxim-ic.com/microcontrollers . ? the maxq2000 errata sheet, available at www.maxim-ic.com/errata . ? the maxq family user? guide , which contains detailed information on core features and operation, including programming. ? the maxq family user? guide: maxq2000 supplement , which contains detailed information on features specific to the maxq2000. seg0 seg1 seg2 seg3 com0 seg0:7 connected to dark grey segments com1 connected to light grey segments seg4 seg5 seg6 seg7 maxq2000 figure 5. two-character, 1/2 duty, lcd interface example
maxq2000 low-power lcd microcontroller ____________________________________________________________________ 33 development and t echnical support a variety of highly versatile, affordably priced development tools for this microcontroller are available from maxim/ dallas semiconductor and third-party suppliers, including: ? compilers ? in-circuit emulators ? integrated development environments (ides) ? jtag-to-serial converters for programming and debugging a partial list of development tool vendors can be found on our website at www.maxim-ic.com/microcontrollers . technical support is available through email at maxq.support@dalsemi.com . 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 seg10/p1.2 seg9/p1.1 seg8/p1.0 seg7/p0.7/int3 seg6/p0.6/int2 seg5/p0.5/int1 seg4/p0.4/int0 seg3/p0.3 seg2/p0.2 seg1/p0.1 seg0/p0.0 51 hfxin hfxout v dd p6.5/t0/wkout1 p6.4/t0b/wkout0 p6.3/t2/ow_in p6.2/t2b/ow_out p6.1/t1/int13 p6.0/t1b/int12 gnd p5.7/miso p5.6/sclk p5.5/mosi p.4/ss p5.3/tx1/int11 p5.2/rx1/int10 32kout seg11/p1.3 top view seg12/p1.4 seg13/p1.5 seg14/p1.6 seg15/p1.7 seg16/p2.0 seg17/p2.1 seg18/p2.2 seg19/p2.3 seg20/p2.4 seg21/p2.5 seg22/p2.6 seg23/p2.7 seg24/p3.0 seg25/p3.1 seg26/p3.2 seg27/p3.3 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 v adj v lcd2 v lcd1 v lcd p7.1/rx0/int15 52 p7.0/tx0/int14 seg28/p3.4/int4 seg29/p3.5/int5 seg30/p3.6/int6 seg31/p3.7/int7 seg32 seg33/com3 seg34/com2 seg35/com1 com0 v ddio gnd p4.0/tck/int8 p4.1/tdi/int9 p4.2/tms p4.3/tdo reset 34 32kin qfn maxq2000 (132-segment lcd) pin configurations
maxq2000 low-power lcd microcontroller 34 ____________________________________________________________________ 56 55 54 53 52 51 50 49 48 47 46 45 44 43 15 16 17 18 19 20 21 22 23 24 25 26 27 28 seg7/p0.7/int3 seg6/p0.6/int2 seg5/p0.5/int1 seg4/p0.4/int0 seg3/p0.3 seg2/p0.2 seg1/p0.1 seg0/p0.0 v adj v lcd2 v lcd1 42 hfxin hfxout v dd p6.5/t0/wkout1 p6.4/t0b/wkout0 p6.1/t1/int13 p6.0/t1b/int12 gnd p5.7/miso p5.6/sclk p5.5/mosi p5.4/ss 32kout 32kin seg8/p1.0 top view seg9/p1.1 seg10/p1.2 seg11/p1.3 seg12/p1.4 seg13/p1.5 seg14/p1.6 seg15/p1.7 seg16/p2.4 seg17/p2.5 seg18/p2.6 seg19/p2.7 seg20/p3.4/int4 seg21/p3.5/int5 41 40 39 38 37 36 35 34 33 32 31 30 29 1 2 3 4 5 6 7 8 9 10 11 12 13 14 v lcd p7.1/rxo/int15 p7.0/txo/int14 seg22/p3.6/int6 seg23/p3.7/int7 seg24 seg25/com3 seg26/com2 seg27/com1 com0 v ddio gnd p4.0/tck/int8 p4.1/tdi/int9 p4.2/tms p4.3/tdo reset tqfn maxq2000 (100-segment lcd) pin configurations (continued)
maxq2000 low-power lcd microcontroller ____________________________________________________________________ 35 glucose microcontroller p7.1rx0/int15 p6.2/t2b/ow_out p5.5/mosi p5.7/miso p5.6/sclk p5.4/ss v ddio v dd gnd gndio v lcd v lcd1 v lcd2 v adj seg4/p0.4/into reset hfxout hfxin p6.3/t2/ow_in p7.0tx0/int14 uart1 serial data download connector +3.3v rs-232 chip +3.3v pc_tx pc_rx tx rx interface cable rs-232 serial port timer 0 data gnd 1-wire eeprom v ss cpout 5k ? 1-wire interface v ddio gnd v ss meter cal parameters and patient data storage cal port connector v lcd (+3.3v) gnd p4.3/tdo p4.0/tck/int8 p6.1/t1/int13 p6.0/t1b/int12 seg31/p3.7/int7 seg29/p3.5/int5 seg[28:5] seg[0:3] seg[32] com[3:1]/seg[35:33] com[0] jtag jtag download/ debug connector v lcd (+3.3v) gndio v ddio gndio p4.2/tms p4.1/tdi/int9 tdo tck piezo buzzer differentially driven at 6.6v and -2khz to 10khz 116 segment lcd glass note that up to 132 lcd segments can be driven if other muxed pin functions are not used tms tdi 4-wire spi interface lcd drivers v ddio max1358 max1359 max1360 din dout sclk upio2 upio4 outa swa fba daca upio3 csi gndio 32kclk v ss v batt v ss v ss 32kin 32.768khz watch xtal glucose meter circuit board 32kout clk32k clk reset int max1358/9/60 interrupt dv dd v ss v ss test strip strip inserted remote temperature measurement diode test strip port connector v ss wakeup charge- pump doubler linear reg bg 32k osc watchdog timer v ss v ddio or gndio v lcd (+3.3v) v ddio 200k ? 200k ? v ss on strip inserted gndio 16-bit risc micro maxq2000 hf osc 32kin 32kout 32khz micro clock (optional) high-frequency micro clock 32k osc rtc and system timers/ alarms 32/64kb flash/ mask p5.2/ rx1/int10 seg30/ p3.6/int6 200k ? 200k ? 200k ? int int int mem up down p5.3/ tx1/int11 v ss gndio av dd dv dd 2 aaa or 1 lithium coin cell (+1.8v to +3.6v) dgnd upi01 cpout regulated +3.3v p6.5/t0/wkout cf+ cf- reg agnd max 1678 1-5mhz fll gnd data 1-wire eprom test strip cal parameters adc outb swb fbb sno1 scm1 snc1 out1 inm1 inp1 ref dacb sno2 scm2 snc2 ain1 ain2 v ddio v ss t ypical operating circuit
maxq2000 low-power lcd microcontroller 36 ____________________________________________________________________ package information (the package drawing(s) in this data sheet may not reflect the most current specifications. for the latest package outline info rmation, go to www.maxim-ic.com/dallaspackinfo ) . 68l qfn.eps c 1 2 21-0122 package outline, 68l qfn, 10x10x0.9 mm
maxq2000 low-power lcd microcontroller ____________________________________________________________________ 37 c 1 2 21-0122 package outline, 68l qfn, 10x10x0.9 mm package information (continued) (the package drawing(s) in this data sheet may not reflect the most current specifications. for the latest package outline info rmation, go to www.maxim-ic.com/dallaspackinfo ) .
maxq2000 low-power lcd microcontroller 38 ____________________________________________________________________ 56l thin qfn.eps package information (continued) (the package drawing(s) in this data sheet may not reflect the most current specifications. for the latest package outline info rmation, go to www.maxim-ic.com/dallaspackinfo ) .
maxq2000 low-power lcd microcontroller maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a maxim product. no circu it patent licenses are implied. maxim reserves the right to change the circuitry and specifications without notice at any time. maxim integrated products, 120 san gabriel drive, sunnyvale, ca 94086 408-737-7600 ____________________ 39 2004 maxim integrated products printed usa is a registered trademark of maxim integrated products. is a registered trademark of dallas semiconductor corporation. package information (continued) (the package drawing(s) in this data sheet may not reflect the most current specifications. for the latest package outline info rmation, go to www.maxim-ic.com/dallaspackinfo ) .

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